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| SY54020AR Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN 3.2Gbps, 3.2GHz General Description The SY54020AR is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable (/EN). The Enable is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. When this device is used as a clock fanout, disabling the downstream clock may reduce system power. The SY54020AR can process clock signals as fast as 3.2 GHz or data patterns up to 3.2Gbps. The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals as small as 100mV (200mVpp) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an internal voltage reference is provided to bias the VT pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 100ps. The SY54020AR operates from a 2.5V 5% core supply and a 1.2V, 1.8V or 2.5V 5% output supply and is guaranteed over the full industrial temperature range (- 40C to +85C). Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com. Precision Edge(R) Features * 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer * Active-low Enable (/EN) input to disable the outputs * Guaranteed AC performance over temperature and voltage: - DC-to > 3.2Gbps Data throughput - DC-to > 3.2GHz Clock throughput - <320 ps propagation delay (IN-to-Q) - <20ps within-device skew - <100 ps rise/fall times * Ultra-low jitter design - <1psRMS cycle-to-cycle jitter * High-speed CML outputs * 2.5V 5% VCC , 1.2/1.8V/2.5V 5% VCCO power supply operation * Industrial temperature range: -40C to +85C * Available in 16-pin (3mm x 3mm) MLF(R) package Applications * SONET clock and data distribution * Fibre Channel clock and data distribution * Gigabit Ethernet clock and data distribution Functional Block Diagram Markets * * * * * * * Storage ATE Test and measurement Enterprise networking equipment High-end servers Access Metro area network equipment Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com April 2009 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Ordering Information(1) Part Number SY54020ARMG SY54020ARMGTR(2) Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. Package Type MLF-16 MLF-16 Operating Range Industrial Industrial Package Marking 020A with Pb-Free bar-line indicator 020A with Pb-Free bar-line indicator Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free Pin Configuration 16-Pin MLF(R) (MLF-16) April 2009 2 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Pin Description Pin Number 2,3 Pin Name IN, /IN Pin Function Differential Input: This input pair is the differential signal input to the device. It accepts differential signals as small as 100mV (200mVPP). Each input pin internally terminates with 50 to the VT pin. Note that this input will default to an indeterminate state if left open. Please refer to the "Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. An internal high impedance resistor divider biases VT to allow input AC-coupling. For AC-coupling, bypass VT with 0.1F low ESR capacitor to VCC. See "Interface Applications" subsection and Figure 2a. Single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. The input switching threshold is Vcc/2. Note that this input is internally connected to a 25k pull-down resistor and will default to a logic LOW state (Enabled) if left open. Outputs are disabled when /EN is high. See Figure 1b for more details. Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC pin as possible. Supplies input and core circuitry. Output Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCCO pins as possible. Supplies the output buffers. Ground: Exposed pad must be connected to a ground plane that is the same potential as the ground pin. CML Differential Output Pairs: Differential buffered copy of the input signal. The output swing is typically 390mV. See "Interface Applications" subsection for termination information. 1 VT 4 /EN 16 8,13 5 15,14 12,11 10,9 7,6 VCC VCCO GND, Exposed pad Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Truth Table IN 0 1 X Note: 1. See timing diagram, Figure 1b. /IN 1 0 X /EN 0 0 1 Q 0 1 0(1) /Q 1 0 1(1) April 2009 3 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Absolute Maximum Ratings(1) Supply Voltage (VCC) ............................... -0.5V to +3.0V Supply Voltage (VCCO) ............................. -0.5V to +2.7V VCC - VCCO ...............................................................<1.8V VCCO - VCC ...............................................................<0.5V Input Voltage (VIN) ............................-0.5V to VCC + 0.5V CML Output Voltage (VOUT) ............... 0.6V to VCCO+0.5V Current (VT) Source or sink current on VT pin .................100mA Input Current Source or sink current on (IN, /IN).................50mA Maximum operating Junction Temperature .......... 125C Lead Temperature (soldering, 20sec.) .................. 260C Storage Temperature (Ts) ....................-65C to +150C Operating Ratings(2) Supply Voltage (VCC) ..............................................2.375V to 2.625V (VCCO) ..............................................1.14V to 2.625V Ambient Temperature (TA) ................... -40C to +85C Package Thermal Resistance(3) MLF(R) Still-air (JA) ............................................ 75C/W Junction-to-board (JB) ......................... 33C/W DC Electrical Characteristics (4) TA = -40C to +85C, unless otherwise stated. Symbol VCC Parameter Power Supply Voltage Range Condition VCC VCCO VCCO VCCO Max. VCC No Load. VCCO 45 90 IN, /IN Min. VIL with VIH = 1.2V IN, /IN VIL with VIH = 1.14V, (1.2V-5%) See Figure 3a See Figure 3b 1.2 0.2 1.14 0.66 0.1 0.2 Min 2.375 1.14 1.7 2.375 Typ 2.5 1.2 1.8 2.5 40 64 50 100 Max 2.625 1.26 1.9 2.625 56 84 55 110 VCC VIH-0.1 VCC VIH-0.1 1.0 2.0 1.28 Units V V V V mA mA V V V V V V V ICC ICCO RIN RDIFF_IN VIH VIL VIH VIL VIN VDIFF_IN VT_IN Notes: Power Supply Current Power Supply Current Input Resistance (IN-to-VT, /IN-to-VT ) Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (|IN - /IN|) Voltage from Input to VT 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. April 2009 4 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR CML Outputs DC Electrical Characteristics(5) VCCO = 1.14V to 1.26V, RL = 50 to VCCO, VCCO = 1.7V to 1.9V; 2.375V to 2.625V, RL = 50 to VCCO or 100 across the outputs, VCC = 2.375V to 2.625V. TA = -40C to +85C, unless otherwise stated. Symbol VOH VOUT VDIFF_OUT ROUT Parameter Output HIGH Voltage Output Voltage Swing Differential Output Voltage Swing Output Source Impedance Condition RL = 50 to VCCO See Figure 3a See Figure 3b Min VCCO-0.020 300 600 45 Typ VCCO-0.010 390 780 50 Max VCCO 475 950 55 Units V mV mV LVTTL/CMOS DC Electrical Characteristics (5) VCC = 2.5V 5%, TA = -40C to +85C, unless otherwise stated. Symbol VIH VIL IIH IIL Note: 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min 2.0 Typ Max VCC 0.8 200 Units V V A A VIH = VCC VIL = 0V -5 75 April 2009 5 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR AC Electrical Characteristics VCCO = 1.14V to 1.26V, RL = 50 to VCCO VCCO = 1.7V to 1.9V, 2.375V to 2.625V, RL = 50 to VCCO or 100 across the outputs. VCC = 2.375V to 2.625V. TA = -40C to +85C, unless otherwise stated. Symbol fMAX tPD tS tH tSKEW Parameter Maximum Data Rate/ Frequency Propagation Delay Setup Time Hold Time Output-to-Output Skew Part-to-Part Skew tJitter Data Clock tR, tF Random Jitter Deterministic Jitter Cycle-to-Cycle Jitter Total Jitter Output Rise/Fall Times (20% to 80%) Duty Cycle Notes: 6. 7. 8. 9. Propagation delay is measured with input tr/tf 300 ps (20% to 80%) Output-to-Output skew is the difference in time between both outputs, receiving data from the same input, for the same temperature, voltage and transition. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges of the respective inputs. Random jitter is measured with a K28.7 pattern, measured at fMAX. 23 Condition NRZ Data VOUT > 200mV IN-to-Q /EN /EN Note 7 Note 8 Note 9 Note 10 Note 11 Note 12 At full output swing. Differential I/O 2.5GHz 3.2GHz Clock VIN > 200mV, Note 6, Figure 1a Min 3.2 3.2 Typ Max Units Gbps GHz 150 220 200 100 8 320 ps ps ps 20 75 1 10 1 10 ps ps psRMS psPP psRMS psPP ps % 35 47 45 60 100 53 55 10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn -Tn+1, where T is the time between rising edges of the output signal. 12. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 10 output edges will deviate by more than the specified peak-to-peak jitter value. 12 April 2009 6 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR CML Output Termination with VCCO 1.8V, 2.5V For VCCO of 1.8V and 2.5V, Figure 5a and Figure 5b, terminate with either 50 to VCCO or 100 differentially across the outputs. See Figure 5c for AC-coupling. Input AC-Coupling The SY54020AR input can accept AC coupling from any driver. Bypass VT with a 0.1F low ESR capacitor to VCC as shown in Figures 4c and 4d. VT has an internal high impedance resistor divider as shown in Figure 2a, to provide a bias voltage for AC-coupling. Interface Applications For Input Interface Applications, see Figures 4a through 4f. For CML Output Termination, see Figures 5a through 5d. CML Output Termination with VCCO 1.2V For VCCO of 1.2V, Figure 5a, terminate the output with 50 to1.2V, DC-coupled, not 100 differentially across the outputs. If AC-coupling is used, Figure 5d, terminate into 50 to 1.2V before the coupling capacitor and then connect to a high value resistor to a reference voltage. Do not AC-couple with internally terminated receiver, such as 50 ANY-IN input. AC coupling will offset the output voltage by 200mV and this offset voltage will be too low for proper driver operation. Any unused output pair needs to be terminated when VCCO is 1.2V. Do not leave floating. April 2009 7 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Timing Diagrams Figure 1a. Propagation Delay Figure 1b. Output Enable/Disable Timing Diagram April 2009 8 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Typical Characteristics VCC = 2.5V, VCCO = 1.2V GND = 0V, VIN = 400mV, RL = 50 to 1.2V, TA = 25C, unless otherwise stated. April 2009 9 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Functional Characteristics VCC = 2.5V, VCCO =1.2V, GND = 0V, VIN = 400mV, RL = 50 to 1.2V, TA = 25C, unless otherwise stated. April 2009 10 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Input and Output Stage Figure 2a. Simplified Differential Input Buffer Figure 2b. Simplified CML Output Buffer Single-Ended and Differential Swings Figure 3a. Single-Ended Swing Figure 3b. Differential Swing April 2009 11 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Input Interface Applications Figure 4a. CML Interface (DC-Coupled, 1.8V, 2.5V) Option: may connect VT to VCC Figure 4b. CML Interface (DC-Coupled, 1.2V) Figure 4c. CML Interface (AC-Coupled) Figure 4d. LVPECL Interface (AC-Coupled) Figure 4e. LVPECL Interface (DC-Coupled) Figure 4f. LVDS Interface April 2009 12 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR CML Output Termination Figure 5a. 1.2V, 1.8V or 2.5V CML DC-Coupled Termination Figure 5b. 1.8V or 2.5V CML DC-Coupled Termination Figure 5c. CML AC-Coupled Termination (VCCO 1.8V or 2.5V ) Figure 5d. CML AC-Coupled Termination (VCCO 1.2V only) April 2009 13 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY54020AR Package Information 16-Pin MLF(R) (3mm x3mm) (MLF-16) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2009 Micrel, Incorporated. April 2009 14 M9999-041409-A hbwhelp@micrel.com or (408) 955-1690 |
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